1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More particularly, the invention is in the field of fabrication of conductive layers and structures in semiconductor wafers.
2. Background Art
Semiconductor devices, such as bipolar transistors and field effect transistors (FETs) that are fabricated using silicon or gallium arsenide technology, continue to increase in frequency, speed, and power. As a result, current semiconductor devices, such as bipolar transistors and FETs that are fabricated in a semiconductor die, also require conductive structures that provide effective, low resistance power and ground routing. For example, applications using bipolar transistors can require conductive structures that provide reduced resistance paths for power and ground routing to respective collector and emitter terminals, while FETs can require conductive structures that provide reduced resistance paths for power and ground routing to respective drain and source terminals.
Conventionally, power and ground routing for semiconductor devices is typically provided by interconnect metal segments that are fabricated in interconnect metal layers within the semiconductor die. However, due to thickness constraints on interconnect metal segments fabricated within the die and space constraints within the die, interconnect metal segments may not provide power and ground conduits with sufficiently low resistance for semiconductor devices that operate at increased power levels.
Thus, there is a need in the art for an effective method for fabricating conductive layers and structure with reduced resistance for power or ground routing for semiconductor devices.